--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:29:43 12/05/2014
-- Design Name:   
-- Module Name:   C:/Users/Francis/Documents/Lectiones/MMXIV Autumnus/CA/cpu/arithtestbench2.vhd
-- Project Name:  cpu
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: arithtest
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY arithtestbench2 IS
END arithtestbench2;
 
ARCHITECTURE behavior OF arithtestbench2 IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT arithtest
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         ram1_we : OUT  std_logic;
         ram1_en : OUT  std_logic;
         ram1_oe : OUT  std_logic;
         ram1_addr : OUT  std_logic_vector(17 downto 0);
         ram1_data : INOUT  std_logic_vector(15 downto 0);
         data_ready : IN  std_logic;
         rdn : INOUT  std_logic;
         wrn : INOUT  std_logic;
         tsre : IN  std_logic;
         tbre : IN  std_logic;
         instruction_test : IN  std_logic_vector(15 downto 0);
         output_test : OUT  std_logic_vector(15 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal data_ready : std_logic := '0';
   signal tsre : std_logic := '0';
   signal tbre : std_logic := '0';
   signal instruction_test : std_logic_vector(15 downto 0) := (others => '0');

	--BiDirs
   signal ram1_data : std_logic_vector(15 downto 0);
   signal rdn : std_logic;
   signal wrn : std_logic;

 	--Outputs
   signal ram1_we : std_logic;
   signal ram1_en : std_logic;
   signal ram1_oe : std_logic;
   signal ram1_addr : std_logic_vector(17 downto 0);
   signal output_test : std_logic_vector(15 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: arithtest PORT MAP (
          clk => clk,
          rst => rst,
          ram1_we => ram1_we,
          ram1_en => ram1_en,
          ram1_oe => ram1_oe,
          ram1_addr => ram1_addr,
          ram1_data => ram1_data,
          data_ready => data_ready,
          rdn => rdn,
          wrn => wrn,
          tsre => tsre,
          tbre => tbre,
          instruction_test => instruction_test,
          output_test => output_test
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;
